1. Field of the Invention
The present invention relates to semiconductor memory devices, and particularly to a random access memory capable of reading and writing of data in a random sequence. More particularly, the present invention relates to an improvement of a buffer circuit for generating an internal write designating signal from an externally applied write designating signal.
2. Description of the Background Art
Semiconductor memory devices include a random access memory capable of writing and reading data in a random sequence. The random access memory is used in various fields as a main storage memory or an image processing memory in a computer. The random access memories are divided, in terms of a requirement of refresh operation of stored data into, static random access memories requiring no refresh operation and dynamic random access memories requiring refresh operation. Although the present invention is applicable to both of the static random access memories and the dynamic random access memories, application in a dynamic random access memory will be described below.
FIG. 1 is a diagram illustrating one example of construction of the entirety of a dynamic random access memory 100. In FIG. 1, dynamic random access memory 100 includes a memory cell array in which dynamic type memory cells MC are arranged in a matrix of rows and columns, an address buffer 5 receiving external address A0--An applied to an address input terminal 15 for generating an internal address, a row decoder 2 responsive to an internal row address from the address buffer 5 for selecting a row of memory cell array 1, and a column decoder 4 responsive to an internal column address from address buffer 5 for selecting a column of memory cell array 1.
The dynamic random access memory 100 further includes sense amplifiers for detecting and amplifying data of memory cells at a row in memory cell array 1 selected-by row decoder 2, and I/O gates connecting a column selected by column decoder 4 to internal data bus 50. In FIG. 1, the sense amplifiers and the I/O gates are expressed as a single block 3.
Dynamic random access memory 100 further includes buffer circuits 6, 7 and 8 for generating various kinds of internal control signals, an output buffer 9a for generating external read data IOi from internal read data on a common data bus 50 and providing it to a data input/output terminal 19, and an input buffer 9b for generating internal write data from the data IOi provided to data input/output terminal 19 and transferring internal data onto common data bus 50.
Buffer circuit 6 generates internal control signals for respectively activating address buffer 5 and the sense amplifier included in block 3 in response to a row address strobe signal/RAS which is a first operation timing defining signal applied to a clock input terminal 16a and a column address strobe signal/CAS which is a second operation timing defining signal applied to a clock input terminal 16b. Buffer circuit 6 is referred to as an internal clock generating buffer circuit hereinafter.
Buffer circuit 7 generates an internal write designating signal .psi.WE in response to a write enable signal/WE which is an external write designating signal applied to an external clock input terminal 17 and an internal control signal/.psi.W from internal clock generating buffer circuit 6 and supplies the generated signal to input buffer 9b. The buffer circuit 7 is referred to as a write enable buffer circuit hereinafter.
Buffer circuit 8 generates an internal read designating signal .psi.OE in response to an output enable signal/OE which is an external output designating signal applied to external clock input terminal 18 and an internal control signal/.psi.O from buffer circuit 6 for internal clock generation and applies the generated signal to output buffer 9a. The internal read designating signal .psi.OE and the internal write designating signal .psi.WE set output buffer 9a and input buffer 9b to an active state, respectively.
In FIG. 1, data input/output terminal 19 is shown inputting/outputting data in a unit of 1 bit. It may be constituted so that data of a plurality of bits are inputted and outputted in parallel from the data input/output terminal 19. The data input/output terminal 19 is assumed to input/output data on a bit by bit basis in the description below. Next, operation of the dynamic random access memory shown in FIG. 1 will be described.
A row address strobe signal/RAS which is a first operation timing defining signal applied to external clock input terminal 16a falls to "L" of an active state, and then dynamic random access memory 100 enters from a precharge state (or a standby state) into a memory operation cycle. Buffer circuit 6 for internal clock generation generates an internal control signal for activating address buffer 5 in response to a row address strobe signal/RAS externally applied. At that time, internal clock generating buffer circuit 6 also generates an internal control signal for activating row decoder 2, though not clearly shown in FIG. 1.
Address buffer 5 captures address A0--An applied to input terminal 15 as a row address in response to an internal control signal from the internal clock generating buffer circuit 6 to generate an internal row address and applied it to and row decoder 2. Row decoder 2 decodes the internal row address to select a corresponding single row in memory cell array 1. Subsequently, a sense amplifier included in block 3 is activated in response to an internal control signal from buffer circuit 6 for internal clock generation, and the data in memory cells on the single row selected by the row decoder 2 are detected and amplified.
Subsequently, a column address strobe signal/CAS which is a second operation timing defining signal applied to external clock input terminal 16b falls to "L" of an active state. Buffer circuit 6 for internal clock generation generates an internal control signal for capturing a column address in response to the column address strobe signal/CAS in the active state. Buffer circuit 6 for internal clock generation then also generates an internal control signal for activating column decoder 4. Address buffer 5, in response to the new internal control signal from buffer circuit 6 for internal clock generation, captures the address A0--An applied to address input terminal 15 as a column address to generate an internal column address and applies it to column decoder 4. Column decoder 4 generates a signal for selecting a single column in memory cell array 1 in response to the internal column address One of I/O gates included in block 3 attains a conductive state in response to the column selection signal from column decoder 4, and the column specified by column decoder 4 in memory cell array 1 is connected to common data bus 50. With the above-described series of processes, the operation of selecting a memory cell in memory cell array 1 is finished.
In reading data, output buffer 9a is activated in response to an internal read designating signal .psi.OE, and external read data is generated from data of a selection memory cell transmitted to common data bus 50, which is transmitted to data input/output terminal 19. The presence/absence of the data outputting operation is set by read designating signal/OE externally applied to external clock input terminal 18. Output enable buffer circuit 8 generates an internal read designating signal .psi.OE in response to an internal control signal/.psi.O from internal clock generating buffer circuit 6 and a read designating signal/OE externally applied to external clock input terminal 18. The internal control signal/.psi.O is generated from internal clock generating buffer circuit 6 when both of row address strobe signal /RAS and a column address strobe signal/CAS applied to external clock input terminals 16a and 16b attain an active state.
In writing data, input buffer 9b is activated in response to an internal write designating signal .psi.WE from write enable buffer circuit 7, and internal write data is generated from data applied to data input/output terminal 19 which is transferred onto common data bus 50. The data on common data bus 50 is transferred onto a column in memory cell array 1 specified by column decoder 4 through I/O gate of block 3. Data is thus written in a memory cell selected by row decoder 2 and column decoder 4.
Internal wire designating signal .psi.WE is generated in response to an external write designating signal/WE applied to external clock input terminal 17 and an internal control signal/.psi.W from buffer circuit 6 for internal clock generation. The internal control signal/.psi.W is generated when both of strobe signals/RAS and /CAS applied to external clock input terminals 16a and 16b attain an active state at "L". The timing at which the internal write designating signal .psi.WE makes transition to the active state is determined according to a later one of timings of transition to activation of column address strobe signal/CAS applied to external clock input terminal 16b and write designating signal/WE applied to external clock input terminal 17. An operation mode in which a signal/WE attains an active state prior to a signal/CAS is referred to as an early write cycle.
As described above, in a structure in which data is inputted and outputted through common terminal 19, by using external write designating signal/WE and read designating signal/OE, collision of data read from the dynamic random access memory 100 and to be written data applied to input/output terminal 19 can be prevented. Also, in order to prevent the collision of written data and read data more reliably, write enable buffer circuit 7 applies an internal write designating signal .psi.WE to output enable buffer circuit 8 and to set the output enable buffer circuit 8 to an output disable state (an inactive state) in writing data. Next, construction and operation of the write enable buffer circuit 7 and the output enable buffer circuit 8 will be described referring to FIG. 2.
FIG. 2 is a block diagram schematically showing constructions of buffer circuit 7 for write enable and buffer circuit 8 for output enable. In FIG. 2, write enable buffer circuit 7 includes a gate circuit 71 receiving a write designating signal/WE applied to external clock input terminal 17 and an internal control signal/.psi.W from buffer circuit 6 for internal clock generation and generating a first internal write designating signal .psi.WE', and a .psi.WE generating circuit 72 generating a second internal write designating signal .psi.WE which attains an active state for a predetermined period in response to an active state of the first internal write designating signal .psi.WE'.
Output enable buffer circuit 8 includes a gate circuit 81 responsive to an output designating signal/OE applied to an external clock input terminal 18 and an internal control signal/.psi.O generated from buffer circuit 6 for internal clock generation to generate a first internal output designating signal .psi.OE', and a .psi.OE generating circuit 82 responsive to a first internal output designating signal .psi.OE' to generate a second internal output designating signal .psi.OE. The .psi.OE generating circuit 82 generates a pulse signal which attains an active state for a predetermined period in response to a rise of the first internal output designating signal .psi.OE'. Also, the .psi.OE generating circuit 82 is brought into an output disable state in response to the second internal write designating signal .psi.WE from .psi.WE generating circuit 72. The output disable state means a condition under which the second internal read designating signal .psi.OE is set to "L" which is an inactive state. Next, operation of the write enable buffer circuit 7 and output enable buffer circuit 8 will be described.
FIG. 3 is a signal waveform diagram indicating operation of the buffer circuits 7 and 8 in data reading. Referring to FIGS. 2 and 3, operation in data reading will be described below. Upon transition of an externally applied row address strobe signal/RAS to an active state "L", the memory cycle of a dynamic random access memory is started. In FIG. 3, a signal external to the dynamic random access memory is indicated with "ext" at the head of the signal. Selection of a row of memory cells in memory cell array 1 (refer to FIG. 1), and detection and amplification of data of the row of memory cells are performed in response to the external row address strobe signal ext/RAS, and then a column address strobe signal ext/CAS from the outside attains an active state.
Upon fall of the external column address strobe signal ext/CAS to "L", internal control signal/.psi.O falls to an active state at "L". Normally, data is read after completion of operation of selecting a memory cell in memory cell array 1, so that an internal control signal/.psi.O is normally not brought to an active state ("L" level) until both of the external signals/RAS and/CAS attains an active state at "L". When both of the internal control signal/.psi.O and an output designating signal/OE applied to external clock input terminal 18 attain "L", a first internal output designating signal .psi.OE' from gate circuit 81 rises to "H". In a data reading mode, a write designating signal/WE applied to external clock input terminal 17 is at an inactive "H" level. Accordingly, both of the first and second internal write designating signals .psi.WE' and .psi.WE are at "L".
.psi.OE generating circuit 82 is brought to an operational state in response to the second internal write designating signal .psi.WE at "L" and the first internal output designating signal .psi.OE' at "H". .psi.OE generating circuit 82 amplifies (or buffers) the first output designating signal .psi.OE' to output a second internal output designating signal .psi.OE. Output buffer 9a is activated in response to the second internal output designating signal .psi.OE, and produces external output data from data supplied onto common data bus 50 and applies the output data to data input/output terminal 19. Valid output data extIOi is outputted from data input/output terminal 19. When one memory cycle is completed and a column address strobe signal/CAS rises to "H", the internal control signal/.psi.O rises to "H" and both of the first and second internal output designating signals .psi.OE' and .psi.OE fall to an inactive state at "L". Output buffer 9a thus attains an inactive state, and sets its output at a high impedance state.
Next, operation of buffer circuits 7 and 8 in data writing will be described referring to FIG. 4 which is an operation waveform diagram thereof The memory cycle is started upon a fall of a row address strobe signal ext/RAS from the outside, The same operations as those in data reading are performed until a memory cell is selected in memory cell array 1. When the column address strobe signal ext/CAS from the outside falls to "L", an internal control signal/.psi.W for writing is generated from buffer circuit 6 for internal clock generation. Gate circuit 71 makes first internal write designating signal .psi.WE' rise to an active state "H" when both of a write designating signal ext/WE applied to external clock input terminal 17 and the internal control signal/.psi.W attain "L". In FIG. 4, a case is shown where the write designating signal ext/WE from the outside falls prior to the falls of the column address strobe signal ext/CAS from the outside. The timing of writing data is determined with a later fall of signals ext/CAS and ext/WE from the outside as described above. Generally, when a data input/output terminal is commonly used for data input and data output, the timing is set so that the write designating signal ext/WE from the outside falls prior to the falling of the column address strobe signal ext/CAS from the outside.
.psi.WE generating circuit 72 generates a write pulse lasting for a predetermined time period, that is, a second internal write designating signal .psi.WE in response to a rise of the first internal write designating signal .psi.WE'. Input buffer 9b is thus activated, captures data IOi applied to data input/output terminal 19 and produces internal write data onto common data bus 50.
Second internal write designating signal .psi.WE is also applied to a control input of .psi.OE generating circuit 82 to bring the .psi.OE generating circuit 82 into an output disable state to inhibit generation of second internal output designating signal .psi.OE. Output buffer 9a is thus set in an output high impedance state, so that write data at data input/output terminal 19 is not subjected to adverse effects from an output of output buffer 9a.
Internal write data on common data bus 50 is written in a selected memory cell through a selected column in memory cell array 1. Subsequently, signals/RAS and /CAS rise to "H" to complete the data write cycle.
Instead of a structure in which generation of an internal output designating signal is inhibited with an internal write designating signal as described above, a construction can be employed in which an internal write designating signal is applied to an output buffer and data output of the data output buffer is inhibited with the internal write designating signal.
FIG. 5 is a diagram showing another construction of a conventional data output buffer. In FIG. 5, data output buffer 90 includes gate circuits G1 and G2 at the first stage and output transistors OT1 and OT2 at the output stage. Gate circuit G1 receives internal read data .phi., first internal read designating signal .psi.WE' and an output of an inverter IV6. Inverter IV6 inverts second internal output designating signal .psi.OE. The gate circuit G1 outputs a signal of "H" only when all of its inputs are at "L". Gate circuit G2 receives an output of the inverter IV3, an output of an inverter IV6 and first internal write designating signal .psi.WE'. Inverter IV3 inverts internal read data .phi..The gate circuit G2 outputs a signal of "H" only when all of its inputs are at "L". Internal read data .phi. is data read out from a memory cell selected by row decoder 2 and column decoder 4 in memory cell array 1 and transferred onto common bus 50.
An output of gate circuit G1 is applied to a gate of output transistor OT1 through inverters IV1 and IV2. An output of gate circuit G2 is transferred to a gate of output transistor OT2 through inverters IV4 and IV5. Inverters IV1 and IV2 and inverters IV4 and IV5 constitute buffers, respectively.
Output transistor OT1 has its one conduction terminal connected to an operation power supply potential Vcc and the other conduction terminal connected to data input/output terminal 19. Output transistor OT2 has its one conduction terminal connected to data input/output terminal 19 and the other conduction terminal connected to the other power supply potential Vss which is ground potential, for example. Next, the operation will be described.
In data reading, first internal write designating signal .psi.WE' is at "L" and the second internal read designating signal .psi.OE is at "H". Accordingly, an output of inverter IV6 is at "L". Gate circuits G1 and G2 are thus brought into enable states, respectively, and gate circuits G1 and G2 operate as inverters. Now, if internal read data .phi. is "0", an output of gate circuit G1 is "1" ("H"), and an output of gate circuit G2 is "0" ("L"). Inverters IV1 and IV2 are mutually connected in a cascade manner, and an output of gate circuit G1 is buffered and transferred to the gate of output transistor OT1. An output of gate circuit G1 is now at "H", so that output transistor OT1 attains an ON state. On the other hand, an output of gate circuit G2 is at "L", and output transistor OT2 which receives an output of the gate circuit G2 at its gate through inverters IV4 and IV5 attains an OFF state. An "H" signal is thus transmitted from operational power supply potential Vcc through output transistor OT1 to data input/output terminal 19.
When internal read data .phi. is "1", output transistor OT1 attains an OFF state and output transistor OT2 attains an ON state. Data input/output terminal 19 is discharged to the other power supply potential Vss level through the output transistor OT2 and the signal potential of data input/output terminal 19 attains "L" accordingly.
The internal read data .phi. and the external read data IOi transmitted to data input/output terminal 19 have logics inverted with each other. This is because, in a dynamic random access memory, bit lines constitute complementary bit line pairs and common data bus 50 is also formed of complementary signal line pair, and output buffer 90 receives data on a signal line of negative logic (signal line on which a signal having its logic inverting from read data).
In data writing, first internal write designating signal .psi.WE' is at "H" and second internal designating signal .psi.OE is at "L". Both of gate circuits G1 and G2 are brought into output disable states and the output signal level thereof is set to "L" regardless of the logic of internal read data .phi.. Both of output transistors OT1 and OT2 attain an OFF state, and an output node of the data output buffer 90 is brought into a high impedance state. Thus, collision between data transmitted onto common data bus 50 and write data transmitted to data input/output terminal 19 is prevented for enabling reliable data writing.
FIG. 6 is a diagram schematically showing structure of an output portion of data output buffer 9a (90) Although specific configuration of the entirety of data output buffer 9a in FIG. 1 is not clearly shown, the circuit construction of data output buffer 9a is obtained by omitting a signal path transmitting an internal write designating signal .psi.WE' in FIG. 5.
Dynamic random access memories are employed, e.g., as main storage devices in computers, in practice. Data input/output terminal 19 is connected to external equipment such as a computer through a signal interconnection 150. In the signal interconnection 150, parasitic capacitance 200 such as interconnection capacitance exists as a matter of course. Transmission of read data to data input/output terminal 19 by output buffer 9a (90) is equivalent to charge/discharge of parasitic capacitance 200 which is associated with the signal interconnection 150. When data of "H" is read from output buffer 9a (90), the parasitic capacitance 200 is charged from operational power supply potential Vcc through output transistor OT1. When output buffer 9a (90) outputs data of "L", the electric charges charged in the parasitic capacitance 200 are discharged to the other power supply potential Vss which is ground potential, for example, through output transistor OT2.
In order to read data in a dynamic random access memory at high speed, the charge/discharge of the parasitic capacitance 200 must be performed at high speed. The discharge of the electric charges of the parasitic capacitance 200 is performed to the other power supply potential Vss. The other power supply potential (hereinafter, simply referred to as ground potential) Vss is used commonly to all the circuits in the dynamic random access memory 100 as shown in FIG. 1. That is, the ground line is set to ground potential Vss from the outside through terminal 155. The ground line 160 has interconnection resistance. The charges of parasitic capacitance 200 are discharged onto ground line 160. Accordingly, with discharged charges from the parasitic capacitance 200, the potential of ground line 160 disadvantageously rises to be a noise in discharging of the parasitic capacitance 200, resulting in malfunctions such as data writing when data reading should be performed.
As to the potential rise of the ground line 160, the amount of charges/discharges at one time becomes larger as the number of input/output bits of devices increases from .times.1 bit structure in which a dynamic random access memory performs data input/output for 1 bit unit, to .times.4 bit structure performing data input/output in 4 bits, .times.8 bit structure, and .times.16 bit structure. The extent of the rise of potential becomes more considerable, accordingly. The malfunctions due to noise (disadvantageous rise of potential in ground lines) in data output will be described in more detail below. In FIG. 7, buffer circuits such as internal clock generating buffer circuit 6, write enable buffer circuit 7, and data output buffer 9a share ground line 160. On the ground line 160, discharge current I from data output buffer 9a flows. External clock generating buffer circuit 6, as shown in FIG. 1, receives row address strobe signal/RAS and column address strobe signal/CAS respectively applied to external clock input terminals 16a and 16b. As shown in FIG. 2, write enable buffer circuit 7 receives a write designating signal/WE from the outside applied to external clock input terminal 17. Normally, a dynamic random access memory has its signal input/output level set to TTL level for matching with external equipment (CPU, controller and so forth) configured with TTL (Transistor.Transistor.Logic) base. In the TTL level, "H" is approximately 2.5 V or higher, and "L" is approximately 0.5 V or lower.
As shown in FIG. 2, gate circuit 71 of write enable buffer circuit 7 receives a write designating signal/WE (ext/WE) externally applied and an internal control signal /.psi.W. The write designating signal/WE from outside is a signal of the TTL level as described above. An input logic threshold voltage of gate circuit 71 is set to the TTL level. The input logic threshold voltage includes the difference between operational power supply potential-Vcc and the other power supply potential Vss as a determination factor thereof. In normal operation, that is, when the other power supply potential Vss is b 0 V, as shown in FIG. 8, the input logic values of gate circuit 71 are set such that about 2.5 V or higher is determined "H" and about 0.5 V or lower is determined "L".
Now, as shown in FIG. 8, it is assumed that the other power supply potential Vss increases by .DELTA.V1 to attain Vss1 with discharge of data output buffer 9a. In this case, an input logic threshold voltage of the gate circuit 71 shifts toward a potential accordingly, and a reference signal potential H' indicating the "H" level and a reference signal potential L' indicating the "L" level also shift toward the high potential accordingly. In this case, the signal potential L' increases to a level between "H" and "L" of the TTL level in normal operation. At that time, there is a possibility that data circuit 71 determines a signal /WE at "H" to be at "L" in data reading and instantly brings a first internal write designating signal .psi.WE' which is its output signal to the "H" level.
When the potential increase of the ground line 160 becomes .DELTA.V2 and the potential Vss becomes Vss2 as shown in FIG. 8, if a signal potential determining "H" and "L" of the gate circuit 71 attains H" and L", the potential level of the signal potential L" is at a level higher than the TTL "H" level in normal operation. In this case, gate circuit 71 determines both of the input signals/WE and /.psi.W to be at "L", and makes the first internal write designating signal .psi.WE' rise to "H". Data output operation where noise (glitch) is caused in a first internal write designating signal .psi.WE' will be described below.
FIG. 9 is a signal waveform diagram showing a data reading operation where glitch is caused in the first internal write designating signal .psi.WE'. In FIG. 9, when a column address strobe signal /CAS (ext/CAS) falls to "L", an internal control signal .psi.O is produced. When both of the internal control signal /.psi.O and an output designate signal/OE (ext/OE) from outside attain "L", a first output designating signal .psi.OE' is produced from gate circuit 81. .psi.OE generating circuit 82 generates a second internal output designating signal .psi.OE in response to the first output designating signal .psi.OE'. Output buffer 9a is activated by the second internal output designating signal .psi.OE, and output data IOi (ext/IOi) is outputted to data input/output terminal 19. The parasitic capacitance 200 is discharged to increase the potential of ground line 160, as shown in FIG. 6, when "L" data is outputted by the operation of output buffer 9a. With the rise of potential of ground line 160, glitch A is produced in the first internal write designating signal .psi.WE' as described above.
.psi.WE generating circuit 72 generates a second internal write designating signal .psi.WE having a predetermined time width t1 in response to the rising edge of the first internal write designating signal .psi.WE'. Accordingly, even if the level of glitch A of the first write designating signal .psi.WE' is very low, .psi.WE generating circuit 72 generates a second internal write designating signal .psi.WE having a predetermined time width t1 in response to the glitch A.
When output enable buffer circuit 8 has the construction shown in FIG. 2, in response to the second internal write designating signal .psi.WE, .psi.OE generating circuit 82 is reset and the second internal output designating signal .psi.OE falls to "L" level. Thus, input buffer 9b operates. On the other hand, an output of output buffer 9a attains a high impedance state. In this case, the read data appearing at data input/output terminal 19 is not held in a sufficient time period (e.g., a data hold time set in specification), and is thus held for a short a time, so that a problem is produced that precise data reading cannot be performed.
Also, as shown in FIG. 2, without resetting of .psi.OE generating circuit 82 with construction of output buffer 90 as shown in FIG. 5, even if a second internal output designating signal .psi.OE is generated, gate circuits G1 and G2 stay in an output disable state for that period due to glitch A of the first internal write designating signal .psi.WE', with a result that an output of data output buffer 90 attains a high impedance state. Even if the period of glitch A of the first internal write designating signal .psi.WE' is very short, data output buffer 90 shown in FIG. 5 also stays in an output high impedance state for that period, so that data reading cannot be performed precisely.
Further, stored data may be decaded because data writing circuitry operates due to the glitch A to write unstable data at data input/output terminal 19 into a selected memory cell.
In order to prevent malfunctions due to the glitch A of a first internal write designating signal .psi.WE' as described above, construction of a write enable buffer circuit as shown in FIG. 10 may be employed. The write enable buffer circuit 170 shown in FIG. 10 is generally used in a static random access memory.
Same reference numerals are assigned to components of the write enable buffer circuit shown in FIG. 10 and corresponding components of the write enable buffer circuit shown in FIG. 2. In FIG. 10, write enable buffer circuit 170 includes a delay circuit 175 for delaying an output of gate circuit 71 for a predetermined time period, a gate circuit 73 for receiving an output of gate circuit 71 and an output of delay circuit 175, and an inverter 74 for receiving an output of gate circuit 73. A first internal write designating signal .psi.WE' is produced from inverter 74. Gate circuit 73 outputs a signal of "L" only when both of the inputs are at "H". Next, operations of the write enable buffer circuit 170 shown in FIG. 10 will be described referring to FIG. 11 which is a waveform diagram of the operation.
An external write designating signal/WE (ext/WE) applied to an external clock input terminal 17 is set at "L" when data is written. Subsequently, after completion of selecting operation of memory cells in a memory cell array, a column address strobe signal/CAS (ext/CAS) from outside falls to "L". In response to the fall to "L" of the column address strobe signal/CAS from outside, an internal control signal/.psi.W falls to "L". Thus, an output of gate circuit 71 rises to "H". An output of delay circuit 175 rises to "H" after a time T has passed since the rise of the output of gate circuit 71. Gate circuit 73 outputs a "L" signal when both of the inputs attain "H". Inverter circuit 74 inverts an output of gate circuit 73. Accordingly, a first internal write designating signal .psi.WE' rises to "H" after a time t2 passes after the signal /CAS falls to "L". In FIG. 11, time T is equal to time t2 or shorter. In FIG. 11, the time t2 is shown considerably longer than time T, but this is because the delay time in gate circuit 73 and inverter circuit 74 is shown exaggerated.
In the circuit construction shown in FIG. 10, in data reading, an external write designating signal/WE applied to clock input terminal 17 is at "H" and an output of gate circuit 71 is "L". Now, an operation where glitch is caused due to the data reading operation in an output of gate circuit 71 will be described referring to FIG. 12 which is a waveform diagram of the operation.
In FIG. 12, a case is considered where glitch A is generated in an output of gate circuit 71 at time Ta. The glitch A is delayed by time T by delay circuit 175. Accordingly, the glitch A' of the output of delay circuit 175 appears at time Tb. An output of gate circuit 73 attains "L" only when both of an output of gate circuit 71 and an output of delay circuit 175 are at "H". Accordingly, even if glitch A is generated in an output of gate circuit 71, the level of an output of gate circuit 73 is "H", and the first internal write designating signal .psi.WE' stays at "L".
Provision of delay circuit 175 as described above can prevent malfunctions due to glitch. However, in the case of the circuit construction shown in FIG. 10, a first internal write designating signal .psi.WE' is generated after a time t2 has passed since a column address strobe signal/CAS (ext/CAS) from the outside attained "L" in data writing operation. A second internal write designating signal .psi.WE is generated for a predetermined time width in response to the first internal write designating signal .psi.WE'. Accordingly, there is a problem that data writing takes a long time. Especially, in a high speed dynamic random access memory, as one cycle time is short, the period of "L" of the write designating signal/WE from outside is also short. In this case, setting of timing is extremely difficult for generating a second internal write designating signal .psi.WE having a sufficient pulse width. If the write pulse width is made short, precise data writing cannot be performed.
A structure for preventing bad influences upon reading operation by noise of write data in data reading is shown in Japanese Patent Laying-Open No. 61-68796. The prior art device includes a write control circuit which prevents transmission of an output of a data writing buffer circuit into a storage element in data reading operation. A write control signal applied to the write control circuit brings the write control circuit in an operational state only in data reading, and brings it-in a non-operational state in data writing. However, in the prior art reference, no structure is shown for preventing a data output buffer from falling into an output high impedance state due to an internal write designating signal in data reading. Also, the prior art reference gives no consideration to glitch caused in a writing control signal due to the data reading operation.